Conventional delay generators that utilize analog replica biasing schemes often include a delay-locked loop (DLL) or phase-locked loop (PLL) to generate a control voltage, which is typically buffered and used to drive delay stages within a delay generator. Unfortunately, these conventional approaches typically require closed loop operation with a running reference, such as an on-chip crystal oscillator (XO), a voltage-controlled oscillator (VCO), dividers, a phase-frequency detector, a charge pump and a loop filter. As will be understood by those skilled in the art, such closed loop operation with a continuously running DLL/PLL/XO can burn significant power and generate spurs to low phase noise clocks. Moreover, to reduce spur coupling, regulators were typically required, which further increased power consumption and chip layout requirements. Alternative approaches have included using digital PLLs to digitize the control voltage generation, followed by a digital-to-analog converter (DAC) to regenerate the control voltage for other components within the delay generator. However, this latter approach was prone to systematic mismatch of control voltages between the DLL/PLL and other delay generating components.
One example of a digital delay line is disclosed in commonly assigned U.S. Pat. Nos. 6,856,558 and 6,944,070 to Proebsting et al., entitled “Integrated Circuit Devices Having High Precision Digital Delay Lines Therein,” the disclosure of which is hereby incorporated herein by reference. In particular, the '558 and '070 patents disclose a delay line control circuit, which generates an injection control signal by counting multiple cycles of a high frequency ring oscillator signal.